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preliminary this document contains information on a product under development at advanced micro devices. the information is intended to help you evaluate this product. amd reserves the right to change or discontinue work on this proposed product without notice. publication# 21524 rev: b amendment/ +1 issue date: march 1998 refer to amds website (www.amd.com) for the latest information. am29lv008b 8 megabit (1 m x 8-bit) cmos 3.0 volt-only boot sector flash memory distinctive characteristics n single power supply operation full voltage range: 2.7 to 3.6 volt read and write operations for battery-powered applications regulated voltage range: 3.0 to 3.6 volt read and write operations and for compatibility with high performance 3.3 volt microprocessors n manufactured on 0.35 m process technology compatible with 0.5 m am29lv008 device n high performance full voltage range: access times as fast as 80 ns regulated voltage range: access times as fast as 70 ns n ultra low power consumption (typical values at 5 mhz) 200 na automatic sleep mode current 200 na standby mode current 7 ma read current 15 ma program/erase current n flexible sector architecture one 16 kbyte, two 8 kbyte, one 32 kbyte, and fifteen 64 kbyte sectors supports full chip erase sector protection features: a hardware method of locking a sector to prevent any program or erase operations within that sector sectors can be locked in-system or via programming equipment temporary sector unprotect feature allows code changes in previously locked sectors n unlock bypass program command reduces overall programming time when issuing multiple program command sequences n top or bottom boot block configurations available n embedded algorithms embedded erase algorithm automatically preprograms and erases the entire chip or any combination of designated sectors embedded program algorithm automatically writes and verifies data at specified addresses n minimum 1,000,000 write cycle guarantee per sector n package option 40-pin tsop n compatibility with jedec standards pinout and software compatible with single- power supply flash superior inadvertent write protection n data# polling and toggle bits provides a software method of detecting program or erase operation completion n ready/busy# pin (ry/by#) provides a hardware method of detecting program or erase cycle completion n erase suspend/erase resume suspends an erase operation to read data from, or program data to, a sector that is not being erased, then resumes the erase operation n hardware reset pin (reset#) hardware method to reset the device to reading array data
2 am29lv008b preliminary general description the am29lv008b is an 8 mbit, 3.0 volt-only flash memory organized as 1,048,576 bytes. the device is offered in a 40-pin tsop package. the byte-wide (x8) data appears on dq7Cdq0. this device requires only a single, 3.0 volt v cc supply to perform read, program, and erase operations. a standard eprom pro- grammer can also be used to program and erase the device. this device is manufactured using amds 0.35 m process technology, and offers all the features and benefits of the am29lv008, which was manufactured using 0.5 m process technology. in addition, the am29lv008b features unlock bypass programming and in-system sector protection/unprotection. the standard device offers access times of 70, 80, 90, and 120 ns, allowing high speed microprocessors to operate without wait states. to eliminate bus conten- tion the device has separate chip enable (ce#), write enable (we#) and output enable (oe#) controls. the device requires only a single 3.0 volt power sup- ply for both read and write functions. internally gener- ated and regulated voltages are provided for the program and erase operations. the device is entirely command set compatible with the jedec single-power-supply flash standard . com- mands are written to the command register using standard microprocessor write timings. register con- tents serve as input to an internal state-machine that controls the erase and programming circuitry. write cycles also internally latch addresses and data needed for the programming and erase operations. reading data out of the device is similar to reading from other flash or eprom devices. device programming occurs by executing the program command sequence. this initiates the embedded program algorithman internal algorithm that auto- matically times the program pulse widths and verifies proper cell margin. the unlock bypass mode facili- tates faster programming times by requiring only two write cycles to program data instead of four. device erasure occurs by executing the erase command sequence. this initiates the embedded erase algo- rithman internal algorithm that automatically prepro- grams the array (if it is not already programmed) before executing the erase operation. during erase, the device automatically times the erase pulse widths and verifies proper cell margin. the host system can detect whether a program or erase operation is complete by observing the ry/by# pin, or by reading the dq7 (data# polling) and dq6 (toggle) status bits . after a program or erase cycle has been completed, the device is ready to read array data or accept another command. the sector erase architecture allows memory sectors to be erased and reprogrammed without affecting the data contents of other sectors. the device is fully erased when shipped from the factory. hardware data protection measures include a low v cc detector that automatically inhibits write opera- tions during power transitions. the hardware sector protection feature disables both program and erase operations in any combination of the sectors of mem- ory. this can be achieved in-system or via program- ming equipment. the erase suspend feature enables the user to put erase on hold for any period of time to read data from, or program data to, any sector that is not selected for erasure. true background erase can thus be achieved. the hardware reset# pin terminates any operation in progress and resets the internal state machine to reading array data. the reset# pin may be tied to the system reset circuitry. a system reset would thus also reset the device, enabling the system microprocessor to read the boot-up firmware from the flash memory. the device offers two power-saving features. when addresses have been stable for a specified amount of time, the device enters the automatic sleep mode . the system can also place the device into the standby mode . power consumption is greatly reduced in both these modes. amds flash technology combines years of flash memory manufacturing experience to produce the highest levels of quality, reliability and cost effective- ness. the device electrically erases all bits within a sector simultaneously via fowler-nor dheim tun- neling. the data is programmed using hot electron injection.
am29lv008b 3 preliminary product selector guide note: see ac characteristics for full specifications. block diagram family part number am29lv008b speed options regulated voltage range: v cc =3.0C3.6 v -70r full voltage range: v cc = 2.7C3.6 v -80 -90 -120 max access time, ns (t acc ) 70 80 90 120 max ce# access time, ns (t ce ) 70 80 90 120 max oe# access time, ns (t oe ) 30 30 35 50 input/output buffers x-decoder y-decoder chip enable output enable logic erase voltage generator pgm voltage generator timer v cc detector state control command register v cc v ss we# ce# oe# stb stb dq0 C dq7 sector switches ry/by# reset# data latch y-gating cell matrix address latch a0Ca19 21524b-1
4 am29lv008b preliminary connection diagrams 1 16 2 3 4 5 6 7 8 17 18 19 20 9 10 11 12 13 14 15 40 25 39 38 37 36 35 34 33 32 31 30 29 28 27 26 24 23 22 21 a16 a5 a15 a14 a13 a12 a11 a9 a8 we# reset# nc ry/by# a18 a7 a6 a4 a3 a2 a1 a17 dq0 v ss nc a19 a10 dq7 dq6 dq5 oe# v ss ce# a0 dq4 v cc v cc nc dq3 dq2 dq1 1 16 2 3 4 5 6 7 8 17 18 19 20 9 10 11 12 13 14 15 40 25 39 38 37 36 35 34 33 32 31 30 29 28 27 26 24 23 22 21 a16 a5 a15 a14 a13 a12 a11 a9 a8 we# reset# nc ry/by# a18 a7 a6 a4 a3 a2 a1 a17 dq0 v ss nc a19 a10 dq7 dq6 dq5 ce# v ss ce# a0 dq4 v cc v cc nc dq3 dq2 dq1 21524b-2 reverse tsop standard tsop
am29lv008b 5 preliminary pin configuration a0Ca19 = 20 addresses dq0Cdq7 = 8 data inputs/outputs ce# = chip enable oe# = output enable we# = write enable reset# = hardware reset pin, active low ry/by# = ready/busy# output v cc = 3.0 volt-only single power supply (see product selector guide for speed options and voltage supply tolerances) v ss = device ground nc = pin not connected internally logic symbol 21524b-3 20 8 dq0Cdq7 a0Ca19 ce# oe# we# reset# ry/by#
6 am29lv008b preliminary ordering information standard products amd standard products are available in several packages and operating ranges. the order number (valid combi- nation) is formed by a combination of the elements below. valid combinations valid combinations list configurations planned to be sup- ported in volume for this device. consult the local amd sales office to confirm availability of specific valid combinations and to check on newly released combinations. device number/description am29lv008b 8 megabit (1 m x 8-bit) cmos flash memory 3.0 volt-only read, program, and erase c e -70r am29lv008b t optional processing blank = standard processing b = burn-in (contact an amd representative for more information) temperature range c= commercial (0c to +70c) i = industrial (C40c to +85c) e = extended (C55c to +125c) package type e = 40-pin thin small outline package (tsop) standard pinout (ts 040) f = 40-pin thin small outline package (tsop) reverse pinout (tsr040) speed option see product selector guide and valid combinations boot code sector architecture t = top sector b = bottom sector valid combinations am29lv008bt-70r, am29lv008bb-70r ec, ei, fc, fi am29lv008bt-80, am29lv008bb-80 ec, ei, ee, fc, fi, fe am29lv008bt-90, am29lv008bb-90 am29lv008bt-120, am29lv008bb-120
am29lv008b 7 preliminary device bus operations this section describes the requirements and use of the device bus operations, which are initiated through the internal command register. the command register itself does not occupy any addressable memory location. the register is composed of latches that store the com- mands, along with the address and data information needed to execute the command. the contents of the register serve as inputs to the internal state machine. the state machine outputs dictate the function of the device. table 1 lists the device bus operations, the inputs and control levels they require, and the resulting output. the following subsections describe each of these operations in further detail. table 1. am29lv008b device bus operations legend: l = logic low = v il , h = logic high = v ih , v id = 12.0 0.5 v, x = dont care, a in = address in, d in = data in, d out = data out notes: 1. addresses are a19Ca0. 2. the sector protect and sector unprotect functions may also be implemented via programming equipment. see the sector protection/unprotection section. requirements for reading array data to read array data from the outputs, the system must drive the ce# and oe# pins to v il . ce# is the power control and selects the device. oe# is the output control and gates array data to the output pins. we# should remain at v ih . the internal state machine is set for reading array data upon device power-up, or after a hardware reset. this ensures that no spurious alteration of the memory content occurs during the power transition. no command is necessary in this mode to obtain array data. standard microprocessor read cycles that assert valid addresses on the device address inputs produce valid data on the device data outputs. the device remains enabled for read access until the command register contents are altered. see reading array data for more information. refer to the ac read operations table for timing specifica- tions and to figure 13 for the timing waveforms. i cc1 in the dc characteristics table represents the active current specification for reading array data. writing commands/command sequences to write a command or command sequence (which includes programming data to the device and erasing sectors of memory), the system must drive we# and ce# to v il , and oe# to v ih . the am29lv008b is manufactured on amds new 0.35 m m process technology and offers an unlock bypass mode to facilitate faster programming. once the device enters the unlock bypass mode, only two write cycles are required to program a byte, instead of four. devices manufactured on amds 0.5 m m process technology re- quire a four-bus-cycle command sequence for each byte programmed. the byte program command sequence section has details on programming data to the device using both standard and unlock bypass command se- quences. an erase operation can erase one sector, multiple sec- tors, or the entire device. tables 2 and 3 indicate the address space that each sector occupies. a sector address consists of the address bits required to uniquely select a sector. the command definitions operation ce# oe# we# reset# addresses (note 1) dq0Cdq7 read l l h h a in d out write l h l h a in d in standby v cc 0.3 v xx v cc 0.3 v x high-z output disable l h h h x high-z reset x x x l x high-z sector protect (note 2) l h l v id sector address, a6 = l, a1 = h, a0 = l d in , d out sector unprotect (note 2) l h l v id sector address, a6 = h, a1 = h, a0 = l d in , d out temporary sector unprotect x x x v id a in d in
8 am29lv008b preliminary section has details on erasing a sector or the entire chip, or suspending/resuming the erase operation. after the system writes the autoselect command sequence, the device enters the autoselect mode. the system can then read autoselect codes from the internal register (which is separate from the memory array) on dq7Cdq0. standard read cycle timings apply in this mode. refer to the autoselect mode and autoselect command sequence sections for more information. i cc2 in the dc characteristics table represents the active current specification for the write mode. the ac characteristics section contains timing specification tables and timing diagrams for write operations. program and erase operation status during an erase or program operation, the system may check the status of the operation by reading the status bits on dq7Cdq0. standard read cycle timings and i cc read specifications apply. refer to write operation status for more information, and to ac characteris- tics for timing diagrams. standby mode when the system is not reading or writing to the device, it can place the device in the standby mode. in this mode, current consumption is greatly reduced, and the outputs are placed in the high impedance state, inde- pendent of the oe# input. the device enters the cmos standby mode when the ce# and reset# pins are both held at v cc 0.3 v. (note that this is a more restricted voltage range than v ih .) if ce# and reset# are held at v ih , but not within v cc 0.3 v, the device will be in the standby mode, but the standby current will be greater. the device requires standard access time (t ce ) for read access when the device is in either of these standby modes, before it is ready to read data. if the device is deselected during erasure or program- ming, the device draws active current until the operation is completed. in the dc characteristics table, i cc3 and i cc4 repre- sents the standby current specification. automatic sleep mode the automatic sleep mode minimizes flash device energy consumption. the device automatically enables this mode when addresses remain stable for t acc + 30 ns. the automatic sleep mode is inde- pendent of the ce#, we#, and oe# control signals. standard address access timings provide new data when addresses are changed. while in sleep mode, output data is latched and always available to the system. i cc5 in the dc characteristics table represents the automatic sleep mode current specification. reset#: hardware reset pin the reset# pin provides a hardware method of reset- ting the device to reading array data. when the reset# pin is driven low for at least a period of t rp , the device immediately terminates any operation in progress, tristates all output pins, and ignores all read/write commands for the duration of the reset# pulse. the device also resets the internal state machine to reading array data. the operation that was interrupted should be reinitiated once the device is ready to accept another command sequence, to ensure data integrity. current is reduced for the duration of the reset# pulse. when reset# is held at v ss 0.3 v, the device draws cmos standby current (i cc4 ). if reset# is held at v il but not within v ss 0.3 v, the standby current will be greater. the reset# pin may be tied to the system reset cir- cuitry. a system reset would thus also reset the flash memory, enabling the system to read the boot-up firmware from the flash memory. if reset# is asserted during a program or erase oper- ation, the ry/by# pin remains a 0 (busy) until the internal reset operation is complete, which requires a time of t ready (during embedded algorithms). the system can thus monitor ry/by# to determine whether the reset operation is complete. if reset# is asserted when a program or erase operation is not executing (ry/by# pin is 1), the reset operation is completed within a time of t ready (not during embedded algo- rithms). the system can read data t rh after the reset# pin returns to v ih . refer to the ac characteristics tables for reset# pa- rameters and to figure 14 for the timing diagram. output disable mode when the oe# input is at v ih , output from the device is disabled. the output pins are placed in the high imped- ance state.
am29lv008b 9 preliminary table 2. am29lv008bt top boot block sector address table table 3. am29lv008bb bottom boot block sector address table sector a19 a18 a17 a16 a15 a14 a13 sector size (kbytes) address range (in hexadecimal) sa00000xxx 64 00000hC0ffffh sa10001xxx 64 10000hC1ffffh sa20010xxx 64 20000hC2ffffh sa30011xxx 64 30000hC3ffffh sa40100xxx 64 40000hC4ffffh sa50101xxx 64 50000hC5ffffh sa60110xxx 64 60000hC6ffffh sa70111xxx 64 70000hC7ffffh sa81000xxx 64 80000hC8ffffh sa91001xxx 64 90000hC9ffffh sa101010xxx 64 a0000hCaffffh sa111011xxx 64 b0000hCbffffh sa121100xxx 64 c0000hCcffffh sa131101xxx 64 d0000hCdffffh sa141110xxx 64 e0000hCeffffh sa1511110xx 32 f0000hCf7fffh sa161111100 8 f8000hCf9fffh sa171111101 8 fa000hCfbfffh sa18111111x 16 fc000hCfffffh sector a19 a18 a17 a16 a15 a14 a13 sector size (kbytes) address range (in hexadecimal) sa0000000x 16 00000h-03fffh sa10000010 8 04000h-05fffh sa20000011 8 06000h-07fffh sa300001xx 32 08000h-0ffffh sa40001xxx 64 10000h-1ffffh sa50010xxx 64 20000h-2ffffh sa60011xxx 64 30000h-3ffffh sa70100xxx 64 40000h-4ffffh sa80101xxx 64 50000h-5ffffh sa90110xxx 64 60000h-6ffffh sa100111xxx 64 70000h-7ffffh sa111000xxx 64 80000h-8ffffh sa121001xxx 64 90000h-9ffffh sa131010xxx 64 a0000h-affffh sa141011xxx 64 b0000h-bffffh sa151100xxx 64 c0000h-cffffh sa161101xxx 64 d0000h-dffffh sa171110xxx 64 e0000h-effffh sa181111xxx 64 f0000h-fffffh
10 am29lv008b preliminary autoselect mode the autoselect mode provides manufacturer and device identification, and sector protection verification, through identifier codes output on dq7Cdq0. this mode is primarily intended for programming equipment to automatically match a device to be programmed with its corresponding programming algorithm. however, the autoselect codes can also be accessed in-system through the command register. when using programming equipment, the autoselect mode requires v id (11.5 v to 12.5 v) on address pin a9. address pins a6, a1, and a0 must be as shown in table 4. in addition, when verifying sector protection, the sector address must appear on the appropriate highest order address bits (see tables 2 and 3). table 4 shows the remaining address bits that are dont care. when all necessary bits have been set as required, the programming equipment may then read the corre- sponding identifier code on dq7Cdq0. to access the autoselect codes in-system, the host system can issue the autoselect command via the command register, as shown in table 5. this method does not require v id . see command definitions for details on using the autoselect mode. table 4. am29lv008b autoselect codes (high voltage method) l = logic low = v il , h = logic high = v ih , sa = sector address, x = dont care. sector protection/unprotection the hardware sector protection feature disables both program and erase operations in any sector. the hard- ware sector unprotection feature re-enables both program and erase operations in previously protected sectors. the device is shipped with all sectors unprotected. amd offers the option of programming and protecting sectors at its factory prior to shipping the device through amds expressflash? service. contact an amd representative for details. it is possible to determine whether a sector is protected or unprotected. see autoselect mode for details. sector protection/unprotection can be implemented via two methods. the primary method requires v id on the reset# pin only, and can be implemented either in-system or via programming equipment. figure 2 shows the algo- rithms and figure 21 shows the waveform. this method uses standard microprocessor bus cycle timing. for sector unprotect, all unprotected sectors must first be protected prior to the first sector unprotect write cycle. the alternate method intended only for programming equipment requires v id on address pin a9 and oe#. this method is compatible with programmer routines written for earlier 3.0 volt-only amd flash devices. details on this method are provided in a supplement, publication number 20875. contact an amd represent- ative to request a copy. description ce# oe# we# a19 to a13 a12 to a10 a9 a8 to a7 a6 a5 to a2 a1 a0 dq7 to dq0 manufacturer id : amd l l h x x v id xlxll 01h device id: am29lv008bt (top boot block) llhxxv id xlxlh 3eh device id: am29lv008bb (bottom boot block) llhxxv id xlxlh 37h sector protection verification l l h sa x v id xlxhl 01h (protected) 00h (unprotected)
am29lv008b 11 preliminary figure 1. in-system sector protect/unprotect algorithms sector protect: write 60h to sector address with a6 = 0, a1 = 1, a0 = 0 set up sector address wait 150 s verify sector protect: write 40h to sector address with a6 = 0, a1 = 1, a0 = 0 read from sector address with a6 = 0, a1 = 1, a0 = 0 start plscnt = 1 reset# = v id wait 1 m s first write cycle = 60h? data = 01h? remove v id from reset# write reset command sector protect complete yes yes no plscnt = 25? yes device failed increment plscnt temporary sector unprotect mode no sector unprotect: write 60h to sector address with a6 = 1, a1 = 1, a0 = 0 set up first sector address wait 15 ms verify sector unprotect: write 40h to sector address with a6 = 1, a1 = 1, a0 = 0 read from sector address with a6 = 1, a1 = 1, a0 = 0 start plscnt = 1 reset# = v id wait 1 m s data = 00h? last sector verified? remove v id from reset# write reset command sector unprotect complete yes no plscnt = 1000? yes device failed increment plscnt temporary sector unprotect mode no all sectors protected? yes protect all sectors: the indicated portion of the sector protect algorithm must be performed for all unprotected sectors prior to issuing the first sector unprotect address set up next sector address no yes no yes no no yes no sector protect algorithm sector unprotect algorithm first write cycle = 60h? protect another sector? reset plscnt = 1 21524b-4
12 am29lv008b preliminary temporary sector unprotect this feature allows temporary unprotection of previ- ously protected sectors to change data in-system. the sector unprotect mode is activated by setting the re- set# pin to v id . during this mode, formerly protected sectors can be programmed or erased by selecting the sector addresses. once v id is removed from the re- set# pin, all the previously protected sectors are protected again. figure 2 shows the algorithm, and figure 20 shows the timing diagrams, for this feature. figure 2. temporary sector unprotect operation hardware data protection the command sequence requirement of unlock cycles for programming or erasing provides data protection against inadvertent writes (refer to table 5 for com- mand definitions). in addition, the following hardware data protection measures prevent accidental erasure or programming, which might otherwise be caused by spurious system level signals during v cc power-up and power-down transitions, or from system noise. low v cc write inhibit when v cc is less than v lko , the device does not ac- cept any write cycles. this protects data during v cc power-up and power-down. the command register and all internal program/erase circuits are disabled, and the device resets. subsequent writes are ignored until v cc is greater than v lko . the system must provide the proper signals to the control pins to prevent uninten- tional writes when v cc is greater than v lko . write pulse glitch protection noise pulses of less than 5 ns (typical) on oe#, ce# or we# do not initiate a write cycle. logical inhibit write cycles are inhibited by holding any one of oe# = v il , ce# = v ih or we# = v ih . to initiate a write cycle, ce# and we# must be a logical zero while oe# is a logical one. power-up write inhibit if we# = ce# = v il and oe# = v ih during power up, the device does not accept commands on the rising edge of we#. the internal state machine is automatically reset to reading array data on power-up. command definitions writing specific address and data commands or sequences into the command register initiates device operations. table 5 defines the valid register command sequences. writing incorrect address and data values or writing them in the improper sequence resets the device to reading array data. all addresses are latched on the falling edge of we# or ce#, whichever happens later. all data is latched on the rising edge of we# or ce#, whichever happens first. refer to the appropriate timing diagrams in the ac characteristics section. reading array data the device is automatically set to reading array data after device power-up. no commands are required to retrieve data. the device is also ready to read array data after completing an embedded program or embedded erase algorithm. after the device accepts an erase suspend command, the device enters the erase suspend mode. the system can read array data using the standard read timings, except that if it reads at an address within erase-suspended sectors, the device outputs status data. after completing a programming operation in the erase suspend mode, the system may once again read array data with the same exception. see erase suspend/erase resume commands for more infor- mation on this mode. the system must issue the reset command to re- enable the device for reading array data if dq5 goes high, or while in the autoselect mode. see the reset command section, next. start perform erase or program operations reset# = v ih temporary sector unprotect completed (note 2) reset# = v id (note 1) notes: 1. all protected sectors unprotected. 2. all previously protected sectors are protected once again. 21524b-5
am29lv008b 13 preliminary see also requirements for reading array data in the device bus operations section for more information. the read operations table provides the read parame- ters, and figure 13 shows the timing diagram. reset command writing the reset command to the device resets the de- vice to reading array data. address bits are dont care for this command. the reset command may be written between the se- quence cycles in an erase command sequence before erasing begins. this resets the device to reading array data. once erasure begins, however, the device ig- nores reset commands until the operation is complete. the reset command may be written between the se- quence cycles in a program command sequence be- fore programming begins. this resets the device to reading array data (also applies to programming in erase suspend mode). once programming begins, however, the device ignores reset commands until the operation is complete. the reset command may be written between the sequence cycles in an autoselect command sequence. once in the autoselect mode, the reset command must be written to return to reading array data (also applies to autoselect during erase suspend). if dq5 goes high during a program or erase operation, writing the reset command returns the device to reading array data (also applies during erase sus- pend). see the applicable ac characteristics for parameters, and to figure 14 for the timing wavrforms. autoselect command sequence the autoselect command sequence allows the host system to access the manufacturer and devices codes, and determine whether or not a sector is protected. table 5 shows the address and data requirements. this method is an alternative to that shown in table 4, which is intended for prom programmers and requires v id on address bit a9. the autoselect command sequence is initiated by writing two unlock cycles, followed by the autoselect command. the device then enters the autoselect mode, and the system may read at any address any number of times, without initiating another command sequence. a read cycle at address xx00h retrieves the manufac- turer code. a read cycle at address xx01h returns the device code. a read cycle containing a sector address (sa) and the address 02h returns 01h if that sector is protected, or 00h if it is unprotected. refer to tables 2 and 3 for valid sector addresses. the system must write the reset command to exit the autoselect mode and return to reading array data. byte program command sequence programming is a four-bus-cycle operation. the pro- gram command sequence is initiated by writing two un- lock write cycles, followed by the program set-up command. the program address and data are written next, which in turn initiate the embedded program al- gorithm. the system is not required to provide further controls or timings. the device automatically provides internally generated program pulses and verifies the programmed cell margin. table 5 shows the address and data requirements for the byte program command sequence. when the embedded program algorithm is complete, the device then returns to reading array data and ad- dresses are no longer latched. the system can deter- mine the status of the program operation by using dq7, dq6, or ry/by#. see write operation status for information on these status bits. any commands written to the device during the embedded program algorithm are ignored. note that a hardware reset immediately terminates the program- ming operation. the byte program command sequence should be reinitiated once the device has reset to reading array data, to ensure data integrity. programming is allowed in any sequence and across sector boundaries. a bit cannot be programmed from a 0 back to a 1. attempting to do so may halt the operation and set dq5 to 1, or cause the data# polling algorithm to indicate the operation was suc- cessful. however, a succeeding read will show that the data is still 0. only erase operations can convert a 0 to a 1. unlock bypass command sequence the unlock bypass feature allows the system to pro- gram bytes or words to the device faster than using the standard program command sequence. the unlock by- pass command sequence is initiated by first writing two unlock cycles. this is followed by a third write cycle containing the unlock bypass command, 20h. the de- vice then enters the unlock bypass mode. a two-cycle unlock bypass program command sequence is all that is required to program in this mode. the first cycle in this sequence contains the unlock bypass program command, a0h; the second cycle contains the program address and data. additional data is programmed in the same manner. this mode dispenses with the initial two unlock cycles required in the standard program command sequence, resulting in faster total program- ming time. the command definitions table shows the requirements for the command sequence. during the unlock bypass mode, only the unlock by- pass program and unlock bypass reset commands are valid. to exit the unlock bypass mode, the system
14 am29lv008b preliminary must issue the two-cycle unlock bypass reset com- mand sequence. the first cycle must contain the data 90h; the second cycle the data 00h. addresses are dont care for both cycles. the device then returns to reading array data. figure 3 illustrates the algorithm for the program oper- ation. see the erase/program operations table in ac characteristics for parameters, and figure 15 for tim- ing diagrams. note: see table 5 for program command sequence. figure 3. program operation chip erase command sequence chip erase is a six bus cycle operation. the chip erase command sequence is initiated by writing two unlock cycles, followed by a set-up command. two additional unlock write cycles are then followed by the chip erase command, which in turn invokes the embedded erase algorithm. the device does not require the system to preprogram prior to erase. the embedded erase algo- rithm automatically preprograms and verifies the entire memory for an all zero data pattern prior to electrical erase. the system is not required to provide any con- trols or timings during these operations. table 5 shows the address and data requirements for the chip erase command sequence. any commands written to the chip during the embedded erase algorithm are ignored. note that a hardware reset during the chip erase operation imme- diately terminates the operation. the chip erase command sequence should be reinitiated once the device has returned to reading array data, to ensure data integrity. the system can determine the status of the erase oper- ation by using dq7, dq6, dq2, or ry/by#. see write operation status for information on these status bits. when the embedded erase algorithm is complete, the device returns to reading array data and addresses are no longer latched. figure 4 illustrates the algorithm for the erase opera- tion. see the erase/program operations tables in ac characteristics for parameters, and to figure 16 for timing diagrams. sector erase command sequence sector erase is a six bus cycle operation. the sector erase command sequence is initiated by writing two unlock cycles, followed by a set-up command. two additional unlock write cycles are then followed by the address of the sector to be erased, and the sector erase command. table 5 shows the address and data requirements for the sector erase command sequence. the device does not require the system to preprogram the memory prior to erase. the embedded erase algo- rithm automatically programs and verifies the sector for an all zero data pattern prior to electrical erase. the system is not required to provide any controls or timings during these operations. after the command sequence is written, a sector erase time-out of 50 s begins. during the time-out period, additional sector addresses and sector erase com- mands may be written. loading the sector erase buffer may be done in any sequence, and the number of sectors may be from one sector to all sectors. the time between these additional cycles must be less than 50 s, otherwise the last address and command might not be accepted, and erasure may begin. it is recom- mended that processor interrupts be disabled during this time to ensure all commands are accepted. the interrupts can be re-enabled after the last sector erase command is written. if the time between additional sector erase commands can be assumed to be less than 50 s, the system need not monitor dq3. any command other than sector erase or erase suspend during the time-out period resets the device to reading array data. the system must rewrite the command sequence and any additional sector addresses and commands. start write program command sequence data poll from system verify data? no yes last address? no yes programming completed increment address embedded program algorithm in progress 21524b-6
am29lv008b 15 preliminary the system can monitor dq3 to determine if the sector erase timer has timed out. (see the dq3: sector erase timer section.) the time-out begins from the rising edge of the final we# pulse in the command sequence. once the sector erase operation has begun, only the erase suspend command is valid. all other commands are ignored. note that a hardware reset during the sector erase operation immediately terminates the operation. the sector erase command sequence should be reinitiated once the device has returned to reading array data, to ensure data integrity. when the embedded erase algorithm is complete, the device returns to reading array data and addresses are no longer latched. the system can determine the status of the erase operation by using dq7, dq6, dq2, or ry/by#. refer to write operation status for infor- mation on these status bits. figure 4 illustrates the algorithm for the erase opera- tion. refer to the erase/program operations tables in the ac characteristics section for parameters, and to figure 16 for timing waveforms. erase suspend/erase resume commands the erase suspend command allows the system to interrupt a sector erase operation and then read data from, or program data to, any sector not selected for erasure. this command is valid only during the sector erase operation, including the 50 s time-out period during the sector erase command sequence. the erase suspend command is ignored if written during the chip erase operation or embedded program algo- rithm. writing the erase suspend command during the sector erase time-out immediately terminates the time-out period and suspends the erase operation. addresses are dont-cares when writing the erase suspend command. when the erase suspend command is written during a sector erase operation, the device requires a maximum of 20 s to suspend the erase operation. however, when the erase suspend command is written during the sector erase time-out, the device immediately ter- minates the time-out period and suspends the erase operation. after the erase operation has been suspended, the system can read array data from or program data to any sector not selected for erasure. (the device erase suspends all sectors selected for erasure.) normal read and write timings and command definitions apply. reading at any address within erase-suspended sectors produces status data on dq7Cdq0. the system can use dq7, or dq6 and dq2 together, to determine if a sector is actively erasing or is erase-sus- pended. see write operation status for information on these status bits. after an erase-suspended program operation is com- plete, the system can once again read array data within non-suspended sectors. the system can determine the status of the program operation using the dq7 or dq6 status bits, just as in the standard program operation. see write operation status for more information. the system may also write the autoselect command sequence when the device is in the erase suspend mode. the device allows reading autoselect codes even at addresses within erasing sectors, since the codes are not stored in the memory array. when the device exits the autoselect mode, the device reverts to the erase suspend mode, and is ready for another valid operation. see autoselect command sequence for more information. the system must write the erase resume command (address bits are dont care) to exit the erase suspend mode and continue the sector erase operation. further writes of the resume command are ignored. another erase suspend command can be written after the device has resumed erasing. notes: 1. see table 5 for erase command sequence. 2. see dq3: sector erase timer for more information. figure 4. erase operation start write erase command sequence data poll from system data = ffh? no yes erasure completed embedded erase algorithm in progress 21524b-7
16 am29lv008b preliminary table 5. am29lv008b command definitions legend: x = dont care ra = address of the memory location to be read. rd = data read from location ra during read operation. pa = address of the memory location to be programmed. addresses latch on the falling edge of the we# or ce# pulse, whichever happens later. pd = data to be programmed at location pa. data latches on the rising edge of we# or ce# pulse, whichever happens first. sa = address of the sector to be verified (in autoselect mode) or erased. address bits a19Ca13 uniquely select any sector. notes: 1. see table 1 for description of bus operations. 2. all values are in hexadecimal. 3. except when reading array or autoselect data, all bus cycles are write operations. 4. address bits a19Ca11 are dont cares for unlock and command cycles. 5. no unlock or command cycles required when reading array data. 6. the reset command is required to return to reading array data when device is in the autoselect mode, or if dq5 goes high (while the device is providing status data). 7. the fourth cycle of the autoselect command sequence is a read cycle. 8. the data is 00h for an unprotected sector and 01h for a protected sector. see autoselect command sequence for more information. 9. the unlock bypass command is required prior to the unlock bypass program command. 10. the unlock bypass reset command is required to return to reading array data when the device is in the unlock bypass mode. 11. the system may read and program in non-erasing sectors, or enter the autoselect mode, when in the erase suspend mode. the erase suspend command is valid only during a sector erase operation. 12. the erase resume command is valid only during the erase suspend mode. command sequence (note 1) bus cycles (notes 2-4) first second third fourth fifth sixth addr data addr data addr data addr data addr data addr data read (note 5) 1 ra rd reset (note 6) 1 xxx f0 auto- select (note 7) manufacturer id 4 555 aa 2aa 55 555 90 x00 01 device id, top boot block 4 555 aa 2aa 55 555 90 x01 3e device id, bottom boot block 4 555 aa 2aa 55 555 90 x01 37 sector protect verify (note 8) 4 555 aa 2aa 55 555 90 (sa) x02 00 01 program 4 555 aa 2aa 55 555 a0 pa pd unlock bypass 3 555 aa 2aa 55 555 20 unlock bypass program (note 9) 2 xxx a0 pa pd unlock bypass reset (note 10) 2 xxx 90 xxx 00 chip erase 6 555 aa 2aa 55 555 80 555 aa 2aa 55 555 10 sector erase 6 555 aa 2aa 55 555 80 555 aa 2aa 55 sa 30 erase suspend (note 11) 1 xxx b0 erase resume (note 12) 1 xxx 30 cycles
am29lv008b 17 preliminary write operation status the device provides several bits to determine the sta- tus of a write operation: dq2, dq3, dq5, dq6, dq7, and ry/by#. table 6 and the following subsections de- scribe the functions of these bits. dq7, ry/by#, and dq6 each offer a method for determining whether a program or erase operation is complete or in progress. these three bits are discussed first. dq7: data# polling the data# polling bit, dq7, indicates to the host system whether an embedded algorithm is in progress or com- pleted, or whether the device is in erase suspend. data# polling is valid after the rising edge of the final we# pulse in the program or erase command se- quence. during the embedded program algorithm, the device outputs on dq7 the complement of the datum pro- grammed to dq7. this dq7 status also applies to pro- gramming during erase suspend. when the embedded program algorithm is complete, the device outputs the datum programmed to dq7. the system must provide the program address to read valid status information on dq7. if a program address falls within a protected sector, data# polling on dq7 is active for ap- proximately 1 s, then the device returns to reading array data. during the embedded erase algorithm, data# polling produces a 0 on dq7. when the embedded erase al- gorithm is complete, or if the device enters the erase suspend mode, data# polling produces a 1 on dq7. this is analogous to the complement/true datum output described for the embedded program algorithm: the erase function changes all the bits in a sector to 1; prior to this, the device outputs the complement, or 0. the system must provide an address within any of the sectors selected for erasure to read valid status in- formation on dq7. after an erase command sequence is written, if all sec- tors selected for erasing are protected, data# polling on dq7 is active for approximately 100 s, then the de- vice returns to reading array data. if not all selected sectors are protected, the embedded erase algorithm erases the unprotected sectors, and ignores the se- lected sectors that are protected. when the system detects dq7 has changed from the complement to true data, it can read valid data at dq7C dq0 on the following read cycles. this is because dq7 may change asynchronously with dq0Cdq6 while output enable (oe#) is asserted low. figure 17, data# polling timings (during embedded algorithms), in the ac characteristics section illustrates this. table 6 shows the outputs for data# polling on dq7. figure 5 shows the data# polling algorithm. dq7 = data? yes no no dq5 = 1? no yes yes fail pass read dq7Cdq0 addr = va read dq7Cdq0 addr = va dq7 = data? start notes: 1. va = valid address for programming. during a sector erase operation, a valid address is an address within any sector selected for erasure. during chip erase, a valid address is any non-protected sector address. 2. dq7 should be rechecked even if dq5 = 1 because dq7 may change simultaneously with dq5. 21524b-8 figure 5. data# polling algorithm
18 am29lv008b preliminary ry/by#: ready/busy# the ry/by# is a dedicated, open-drain output pin that indicates whether an embedded algorithm is in progress or complete. the ry/by# status is valid after the rising edge of the final we# pulse in the command sequence. since ry/by# is an open-drain output, sev- eral ry/by# pins can be tied together in parallel with a pull-up resistor to v cc . if the output is low (busy), the device is actively erasing or programming. (this includes programming in the erase suspend mode.) if the output is high (ready), the device is ready to read array data (including during the erase suspend mode), or is in the standby mode. table 6 shows the outputs for ry/by#. figures 13, 14, 15 and 16 shows ry/by# for read, reset, program, and erase operations, respectively. dq6: toggle bit i toggle bit i on dq6 indicates whether an embedded program or erase algorithm is in progress or complete, or whether the device has entered the erase suspend mode. toggle bit i may be read at any address, and is valid after the rising edge of the final we# pulse in the command sequence (prior to the program or erase op- eration), and during the sector erase time-out. during an embedded program or erase algorithm op- eration, successive read cycles to any address cause dq6 to toggle. (the system may use either oe# or ce# to control the read cycles.) when the operation is complete, dq6 stops toggling. after an erase command sequence is written, if all sec- tors selected for erasing are protected, dq6 toggles for approximately 100 s, then returns to reading array data. if not all selected sectors are protected, the em- bedded erase algorithm erases the unprotected sec- tors, and ignores the selected sectors that are protected. the system can use dq6 and dq2 together to deter- mine whether a sector is actively erasing or is erase- suspended. when the device is actively erasing (that is, the embedded erase algorithm is in progress), dq6 toggles. when the device enters the erase suspend mode, dq6 stops toggling. however, the system must also use dq2 to determine which sectors are erasing or erase-suspended. alternatively, the system can use dq7 (see the subsection on dq7: data# polling). if a program address falls within a protected sector, dq6 toggles for approximately 1 s after the program command sequence is written, then returns to reading array data. dq6 also toggles during the erase-suspend-program mode, and stops toggling once the embedded pro- gram algorithm is complete. table 6 shows the outputs for toggle bit i on dq6. refer to figure 6 shows the toggle bit algorithm and to figure 18 in the ac characteristics section for the timing diagrams. figure 19 shows the differences be- tween dq2 and dq6 in graphical form. see also the subsection on dq2: toggle bit ii. dq2: toggle bit ii the toggle bit ii on dq2, when used with dq6, indi- cates whether a particular sector is actively erasing (that is, the embedded erase algorithm is in progress), or whether that sector is erase-suspended. toggle bit ii is valid after the rising edge of the final we# pulse in the command sequence. dq2 toggles when the system reads at addresses within those sectors that have been selected for eras- ure. (the system may use either oe# or ce# to control the read cycles.) but dq2 cannot distinguish whether the sector is actively erasing or is erase-suspended. dq6, by comparison, indicates whether the device is actively erasing, or is in erase suspend, but cannot distinguish which sectors are selected for erasure. thus, both status bits are required for sector and mode information. refer to table 6 to compare outputs for dq2 and dq6. figure 6 shows the toggle bit algorithm in flowchart form, and the section dq2: toggle bit ii explains the algorithm. see also the dq6: toggle bit i subsection. refer to figure 18 for the toggle bit timing diagram. fig- ure 19 shows the differences between dq2 and dq6 in graphical form. reading toggle bits dq6/dq2 refer to figure 6 for the following discussion. whenever the system initially begins reading toggle bit status, it must read dq7Cdq0 at least twice in a row to determine whether a toggle bit is toggling. typically, the system would note and store the value of the toggle bit after the first read. after the second read, the system would com- pare the new value of the toggle bit with the first. if the toggle bit is not toggling, the device has completed the program or erase operation. the system can read array data on dq7Cdq0 on the following read cycle. however, if after the initial two read cycles, the system determines that the toggle bit is still toggling, the sys- tem also should note whether the value of dq5 is high (see the section on dq5). if it is, the system should then determine again whether the toggle bit is toggling, since the toggle bit may have stopped toggling just as dq5 went high. if the toggle bit is no longer toggling, the device has successfully completed the program or erase operation. if it is still toggling, the device did not completed the operation successfully, and the system must write the reset command to return to reading array data.
am29lv008b 19 preliminary the remaining scenario is that the system initially de- termines that the toggle bit is toggling and dq5 has not gone high. the system may continue to monitor the toggle bit and dq5 through successive read cycles, de- termining the status as described in the previous para- graph. alternatively, it may choose to perform other system tasks. in this case, the system must start at the beginning of the algorithm when it returns to determine the status of the operation (top of figure 6). dq5: exceeded timing limits dq5 indicates whether the program or erase time has exceeded a specified internal pulse count limit. under these conditions dq5 produces a 1. this is a failure condition that indicates the program or erase cycle was not successfully completed. the dq5 failure condition may appear if the system tries to program a 1 to a location that is previously programmed to 0. only an erase operation can change a 0 back to a 1. under this condition, the device halts the operation, and when the operation has exceeded the timing limits, dq5 produces a 1. under both these conditions, the system must issue the reset command to return the device to reading array data. dq3: sector erase timer after writing a sector erase command sequence, the system may read dq3 to determine whether or not an erase operation has begun. (the sector erase timer does not apply to the chip erase command.) if additional sectors are selected for erasure, the entire time-out also applies after each additional sector erase command. when the time-out is complete, dq3 switches from 0 to 1. the system may ignore dq3 if the system can guarantee that the time between additional sector erase commands will always be less than 50 m s. see also the sector erase command sequence section. after the sector erase command sequence is written, the system should read the status on dq7 (data# poll- ing) or dq6 (toggle bit i) to ensure the device has ac- cepted the command sequence, and then read dq3. if dq3 is 1, the internally controlled erase cycle has be- gun; all further commands (other than erase suspend) are ignored until the erase operation is complete. if dq3 is 0, the device will accept additional sector erase commands. to ensure the command has been accepted, the system software should check the status of dq3 prior to and following each subsequent sector erase command. if dq3 is high on the second status check, the last command might not have been ac- cepted. table 6 shows the outputs for dq3. start no yes yes dq5 = 1? no yes toggle bit = toggle? no program/erase operation not complete, write reset command program/erase operation complete read dq7Cdq0 toggle bit = toggle? read dq7Cdq0 twice read dq7Cdq0 notes: 1. read toggle bit twice to determine whether or not it is toggling. see text. 2. recheck toggle bit because it may stop toggling as dq5 changes to 1 . see text. 21524b-9 figure 6. toggle bit algorithm (notes 1, 2) (note 1)
20 am29lv008b preliminary table 6. write operation status notes: 1. dq5 switches to 1 when an embedded program or embedded erase operation has exceeded the maximum timing limits. see dq5: exceeded timing limits for more information. 2. dq7 and dq2 require a valid address when reading status information. refer to the appropriate subsection for further details. operation dq7 (note 2) dq6 dq5 (note 1) dq3 dq2 (note 2) ry/by# standard mode embedded program algorithm dq7# toggle 0 n/a no toggle 0 embedded erase algorithm 0 toggle 0 1 toggle 0 erase suspend mode reading within erase suspended sector 1 no toggle 0 n/a toggle 1 reading within non-erase suspended sector data data data data data 1 erase-suspend-program dq7# toggle 0 n/a n/a 0
am29lv008b 21 preliminary absolute maximum ratings storage temperature plastic packages . . . . . . . . . . . . . . . C65 c to +150 c ambient temperature with power applied. . . . . . . . . . . . . . C65 c to +125 c voltage with respect to ground v cc (note 1) . . . . . . . . . . . . . . . . C0.5 v to +4.0 v a9 , oe# , and reset# (note 2). . . . . . . . . . . . C0.5 v to +12.5 v all other pins (note 1) . . . . . C0.5 v to v cc +0.5 v output short circuit current (note 3) . . . . . . 200 ma notes: 1. minimum dc voltage on input or i/o pins is C0.5 v. during voltage transitions, input or i/o pins may undershoot v ss to C2.0 v for periods of up to 20 ns. see figure 7. maximum dc voltage on input or i/o pins is v cc +0.5 v. during voltage transitions, input or i/o pins may overshoot to v cc +2.0 v for periods up to 20 ns. see figure 8. 2. minimum dc input voltage on pins a9, oe#, and reset# is C0.5 v. during voltage transitions, a9, oe#, and reset# may undershoot v ss to C2.0 v for periods of up to 20 ns. see figure 7. maximum dc input voltage on pin a9 is +12.5 v which may overshoot to 14.0 v for periods up to 20 ns. 3. no more than one output may be shorted to ground at a time. duration of the short circuit should not be greater than one second. stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational sections of this data sheet is not implied. exposure of the device to absolute maximum rating conditions for extended periods may affect device reliability. figure 7. maximum negative overshoot waveform figure 8. maximum positive overshoot waveform operating ranges commercial (c) devices ambient temperature (t a ) . . . . . . . . . . . 0c to +70c industrial (i) devices ambient temperature (t a ) . . . . . . . . . C40c to +85c extended (e) devices ambient temperature (t a ) . . . . . . . . C55c to +125c v cc supply voltages v cc for regulated voltage range. . . . .+3.0 v to +3.6 v v cc for full voltage range . . . . . . . . . .+2.7 v to +3.6 v operating ranges define those limits between which the func- tionality of the device is guaranteed. 20 ns 20 ns +0.8 v C0.5 v 20 ns C2.0 v 21524b-10 20 ns 20 ns v cc +2.0 v v cc +0.5 v 20 ns 2.0 v 21524b-11
22 am29lv008b preliminary dc characteristics cmos compatible notes: 1. the i cc current listed is typically less than 2 ma/mhz, with oe# at v ih . typical v cc is 3.0 v. 2. i cc active while embedded erase or embedded program is in progress. 3. automatic sleep mode enables the low power mode when addresses remain stable for t acc + 30 ns. 4. not 100% tested. parameter description test conditions min typ max unit i li input load current v in = v ss to v cc , v cc = v cc max 1.0 a i lit a9 input load current v cc = v cc max ; a9 = 12.5 v 35 a i lo output leakage current v out = v ss to v cc , v cc = v cc max 1.0 a i cc1 v cc active read current (note 1) ce# = v il, oe# = v ih 5 mhz 7 12 ma 1 mhz 2 4 i cc2 v cc active write current (notes 2 and 4) ce# = v il, oe# = v ih 15 30 ma i cc3 v cc standby current v cc = v cc max ; ce#, reset# = v cc 0.3 v 0.2 5 a i cc4 v cc standby current during reset v cc = v cc max ; reset# = v ss 0.3 v 0.2 5 a i cc5 automatic sleep mode (note 3) v ih = v cc 0.3 v; v il = v ss 0.3 v 0.2 5 a v il input low voltage C0.5 0.8 v v ih input high voltage 0.7 x v cc v cc + 0.3 v v id voltage for autoselect and temporary sector unprotect v cc = 3.3 v 11.5 12.5 v v ol output low voltage i ol = 4.0 ma, v cc = v cc min 0.45 v v oh1 output high voltage i oh = C2.0 ma, v cc = v cc min 0.85 v cc v v oh2 i oh = C100 a, v cc = v cc min v cc C0.4 v lko low v cc lock-out voltage (note 4) 2.3 2.5 v
am29lv008b 23 preliminary dc characteristics (continued) zero power flash 20 15 10 5 0 0 500 1000 1500 2000 2500 3000 3500 4000 supply current in ma time in ns note: addresses are switching at 1 mhz 21524b-12 figure 9. i cc1 current vs. time (showing active and automatic sleep currents) 10 8 2 0 12345 frequency in mhz supply current in ma note: t = 25 c 21524b-13 figure 10. typical i cc1 vs. frequency 2.7 v 3.6 v 4 6
24 am29lv008b preliminary test conditions table 7. test specifications key to switching waveforms 2.7 k w c l 6.2 k w 3.3 v device under te s t 21524b-14 figure 11. test setup note: diodes are in3064 or equivalent test condition -70r, -80 -90, -120 unit output load 1 ttl gate output load capacitance, c l (including jig capacitance) 30 100 pf input rise and fall times 5 ns input pulse levels 0.0C3.0 v input timing measurement reference levels 1.5 v output timing measurement reference levels 1.5 v ks000010-pal waveform inputs outputs steady changing from h to l changing from l to h dont care, any change permitted changing, state unknown does not apply center line is high impedance state (high z) 3.0 v 0.0 v 1.5 v 1.5 v output measurement level input 21524b-15 figure 12. input waveforms and measurement levels
am29lv008b 25 preliminary ac characteristics read operations notes: 1. not 100% tested. 2. see figure 11 and table 7 for test specifications. parameter description speed option jedec std test setup -70r -80 -90 -120 unit t avav t rc read cycle time (note 1) min 70 80 90 120 ns t avqv t acc address to output delay ce# = v il oe# = v il max 70 80 90 120 ns t elqv t ce chip enable to output delay oe# = v il max 70 80 90 120 ns t glqv t oe output enable to output delay max 30 30 35 50 ns t ehqz t df chip enable to output high z (note 1) max 25 25 30 30 ns t ghqz t df output enable to output high z (note 1) max 25 25 30 30 ns t oeh output enable hold time (note 1) read min 0 ns toggle and data# polling min 10 ns t axqx t oh output hold time from addresses, ce# or oe#, whichever occurs first (note 1) min 0 ns t ce outputs we# addresses ce# oe# high z output valid high z addresses stable t rc t acc t oeh t oe 0 v ry/by# reset# t df t oh 21524b-16 figure 13. read operations timings
26 am29lv008b preliminary ac characteristics hardware reset (reset#) note: not 100% tested. parameter description all speed options jedec std test setup unit t ready reset# pin low (during embedded algorithms) to read or write (see note) max 20 s t ready reset# pin low (not during embedded algorithms) to read or write (see note) max 500 ns t rp reset# pulse width min 500 ns t rh reset# high time before read (see note) min 50 ns t rpd reset# low to standby mode min 20 s t rb ry/by# recovery time min 0 ns reset# ry/by# ry/by# t rp t ready reset timings not during embedded algorithms t ready ce#, oe# t rh ce#, oe# reset timings during embedded algorithms reset# t rp t rb 21524b-17 figure 14. reset# timings
am29lv008b 27 preliminary ac characteristics erase/program operations notes: 1. not 100% tested. 2. see the erase and programming performance section for more information. parameter -70r -80 -90 -120 jedec std description unit t avav t wc write cycle time (note 1) min 70 80 90 120 ns t avwl t as address setup time min 0 ns t wlax t ah address hold time min 45 45 45 50 ns t dvwh t ds data setup time min 35 35 45 50 ns t whdx t dh data hold time min 0 ns t oes output enable setup time min 0 ns t ghwl t ghwl read recovery time before write (oe# high to we# low) min 0 ns t elwl t cs ce# setup time min 0 ns t wheh t ch ce# hold time min 0 ns t wlwh t wp write pulse width min 35 35 35 50 ns t whwl t wph write pulse width high min 30 ns t whwh1 t whwh1 programming operation (note 2) typ 9 s t whwh2 t whwh2 sector erase operation (note 2) typ 0.7 sec t vcs v cc setup time (note 1) min 50 s t rb recovery time from ry/by# min 0 ns t busy program/erase valid to ry/by# delay min 90 ns
28 am29lv008b preliminary ac characteristics oe# we# ce# v cc data addresses t ds t ah t dh t wp pd t whwh1 t wc t as t wph t vcs 555h pa pa read status data (last two cycles) a0h t ghwl t cs status d out program command sequence (last two cycles) ry/by# t rb t busy t ch pa note: pa = program address, pd = program data, d out is the true data at the program address. 21524b-18 figure 15. program operation timings
am29lv008b 29 preliminary ac characteristics oe# ce# addresses v cc we# data 2aah sa t ghwl t ah t wp t wc t as t wph 555h for chip erase 10 for chip erase 30h t ds t vcs t cs t dh 55h t ch in progress complete t whwh2 va va erase command sequence (last two cycles) read status data ry/by# t rb t busy note: sa = sector address (for sector erase), va = valid address for reading status data (see write operation sta tus). 21524b-19 figure 16. chip/sector erase operation timings
30 am29lv008b preliminary ac characteristics we# ce# oe# high z t oe high z dq7 dq0Cdq6 ry/by# t busy complement true addresses va t oeh t ce t ch t oh t df va va status data complement status data true valid data valid data t acc t rc note: va = valid address. illustration shows first status cycle after command sequence, last status read cycle, and array data read cycle. 21524b-20 figure 17. data# polling timings (during embedded algorithms) we# ce# oe# high z t oe dq6/dq2 ry/by# t busy addresses va t oeh t ce t ch t oh t df va va t acc t rc valid data valid status valid status (first read) (second read) (stops toggling) valid status va note: va = valid address; not required for dq6. illustration shows first two status cycle after command sequence, last status read cycle, and array data read cycle. 21524b-21 figure 18. toggle bit timings (during embedded algorithms)
am29lv008b 31 preliminary ac characteristics temporary sector unprotect note: not 100% tested. parameter all speed options jedec std description unit t vidr v id rise and fall time (see note) min 500 ns t rsp reset# setup time for temporary sector unprotect min 4 s note: the system may use ce# or oe# to toggle dq2 and dq6. dq2 toggles only when read at an address within an erase-suspended sector. 21524b-22 figure 19. dq2 vs. dq6 enter erase erase erase enter erase suspend program erase suspend read erase suspend read erase we# dq6 dq2 erase complete erase suspend suspend program resume embedded erasing reset# t vidr 12 v 0 or 3 v ce# we# ry/by# t vidr t rsp program or erase command sequence 0 or 3 v 21524b-23 figure 20. temporary sector unprotect timing diagram
32 am29lv008b preliminary ac characteristics sector protect: 100 s sector unprot ect: 10 ms 1 s reset# sa, a6, a1, a0 data ce# we# oe# 60h 60h 40h valid* valid* valid* status sector protect/unprotect verify v id v ih * for sector protect, a6 = 0, a1 = 1, a0 = 0. for sector unprotect, a6 = 1, a1 = 1, a0 = 0. 21524b-24 figure 21. sector protect/unprotect timing diagram
am29lv008b 33 preliminary ac characteristics alternate ce# controlled erase/program operations notes: 1. not 100% tested. 2. see the erase and programming performance section for more information. parameter 70r 80 90 120 jedec std description unit t avav t wc write cycle time (note 1) min 70 80 90 120 ns t avel t as address setup time min 0 ns t elax t ah address hold time min 45 45 45 50 ns t dveh t ds data setup time min 35 35 45 50 ns t ehdx t dh data hold time min 0 ns t oes output enable setup time min 0 ns t ghel t ghel read recovery time before write (oe# high to we# low) min 0 ns t wlel t ws we# setup time min 0 ns t ehwh t wh we# hold time min 0 ns t eleh t cp ce# pulse width min 35 35 35 50 ns t ehel t cph ce# pulse width high min 30 ns t whwh1 t whwh1 programming operation (note 2) ty p 9 s t whwh2 t whwh2 sector erase operation (note 2) typ 0.7 sec
34 am29lv008b preliminary ac characteristics t ghel t ws oe# ce# we# reset# t ds data t ah addresses t dh t cp dq7# d out t wc t as t cph pa data# polling a0 for program 55 for erase t rh t whwh1 or 2 ry/by# t wh pd for program 30 for sector erase 10 for chip erase 555 for program 2aa for erase pa for program sa for sector erase 555 for chip erase t busy notes: 1. pa = program address, pd = program data, dq7# = complement of the data written to the device, d out is the data written to the device. 2. figure indicates the last two bus cycles of the command sequence. 21524b-25 figure 22. alternate ce# controlled write operation timings
am29lv008b 35 preliminary erase and programming performance notes: 1. typical program and erase times assume the following conditions: 25 c, 3.0 v v cc , 1,000,000 cycles. additionally, programming typicals assume checkerboard pattern. 2. under worst case conditions of 90c, v cc = 2.7 v, 1,000,000 cycles. 3. the typical chip programming time is considerably less than the maximum chip programming time listed, since most bytes program faster than the maximum program times listed. 4. in the pre-programming step of the embedded erase algorithm, all bytes are programmed to 00h before erasure. 5. system-level overhead is the time required to execute the four-bus-cycle sequence for the program command. see table 5 for further information on command definitions. 6. the device has a minimum erase and program cycle endurance of 1,000,000 cycles. latchup characteristics includes all pins except v cc . test conditions: v cc = 3.0 v, one pin at a time. tsop pin capacitance notes: 1. sampled, not 100% tested. 2. test conditions t a = 25c, f = 1.0 mhz. data retention parameter typ (note 1) max (note 2) unit comments sector erase time 0.7 15 s excludes 00h programming prior to erasure (note 4) chip erase time 14 s byte programming time 9 300 s excludes system level overhead (note 5) chip programming time (note 3) 927s description min max input voltage with respect to v ss on all pins except i/o pins (including a9, oe#, and reset#) C1.0 v 12.5 v input voltage with respect to v ss on all i/o pins C1.0 v v cc + 1.0 v v cc current C100 ma +100 ma parameter symbol parameter description test setup typ max unit c in input capacitance v in = 0 6 7.5 pf c out output capacitance v out = 0 8.5 12 pf c in2 control pin capacitance v in = 0 7.5 9 pf parameter test conditions min unit minimum pattern data retention time 150 c 10 years 125 c 20 years
36 am29lv008b preliminary physical dimensions* ts 04040-pin standard tsop (measured in millimeters) * for reference only. bsc is an ansi standard for basic space centering. 18.30 18.50 19.80 20.20 40 20 pin 1 i.d. 21 1 0.50 bsc 9.90 10.10 0.95 1.05 0.05 0.15 1.20 max 0.50 0.70 0? 5? 16-038-tsop-1_ae ts 040 2-27-97 lv 0.10 0.21 0.08 0.20
am29lv008b 37 preliminary physical dimensions tsr04040-pin reverse tsop (measured in millimeters) * for reference only. bsc is an ansi standard for basic space centering. 18.30 18.50 19.80 20.20 40 20 pin 1 i.d. 21 1 0.50 bsc 9.90 10.10 0.95 1.05 0.05 0.15 1.20 max 0.50 0.70 0? 5? 16-038-tsop-1_ae tsr040 2-27-97 lv 0.10 0.21 0.08 0.20
38 am29lv008b preliminary revision summary for am29lv008b revision b distinctive characteristics changed typical read and program/erase current spec- ifications. device now has a guaranteed minimum endurance of 1,000,000 write cycles. figure 1, in-system sector protect/unprotect algorithm corrected a6 to 0, changed wait specification to 150 s on sector protect and 15 ms on sector unprotect. dc characteristics changed typical read and program/erase current spec- ifications. ac characteristics alternate ce# controlled erase/program operations: changed t cp to 35 ns for 70r, 80, and 90 speed options. erase and programming performance device now has a guaranteed minimum endurance of 1,000,000 write cycles. revision b+1 figure 1, in-system sector protect/unprotect algorithms in the sector protect algorithm, added a reset plscnt=1 box in the path from protect another sec- tor? back to setting up the next sector address. dc characteristics changed note 1 to indicate that oe# is at v ih for the listed current. ac characteristics: erase/program operations; alternate ce# controlled erase/program operations: corrected the notes refer- ence for t whwh1 and t whwh2 . these parameters are 100% tested. corrected the note reference for t vcs . this parameter is not 100% tested. temporary sector unprotect table added note reference for t vidr . this parameter is not 100% tested. figure 21, sector protect/unprotect timing diagram a valid address is not required for the first write cycle; only the data 60h. erase and programming performance in note 2, the worst case endurance is now 1 million cy- cles. trademarks copyright ? 1998 advanced micro devices, inc. all rights reserved. amd, the amd logo, and combinations thereof are registered trademarks of advanced micro devices, inc. expressflash is a trademark of advanced micro devices, inc. product names used in this publication are for identification purposes only and may be trademarks of their respective companies .

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